1. Field of the Invention
The present invention relates to a process for the fabrication of integrated devices in small-thickness semiconductor chips.
2. Description of the Related Art
As is known, customary techniques of fabrication of semiconductor integrated devices (typically micro-electromechanical circuits or devices) envisage providing a plurality of units identical to one another on the same semiconductor wafer. At the end of the process, the so-called “singling” is carried out, i.e., the wafer is divided into a plurality of portions (dice), each of which contains a respective device. Hereinafter, the portions obtained by cutting of a semiconductor wafer will be indicated for reasons of simplicity by the term “chips”.
Normally, a saw is used to cut the wafer.
Prior to singling, the wafer is normally thinned out, so as to reduce as much as possible the thickness of the chips containing the finished devices. This operation enables various advantages to be achieved. In the first place, thin chips have a lower thermal capacitance and a higher thermal conductivity and hence enable a better heat dispersion, which is particularly important when the integrated devices in the chips dissipate high power levels. Furthermore, minimizing the dimensions of the chips in general enables a considerable reduction in the overall dimensions of the devices after packaging in the external protective structures, especially in the case of devices with a number of stacked chips. In some devices, moreover, the current can flow also between the front and rear faces of the chip (vertical-current-flow devices). In this case, the reduction of the thickness also involves a reduction in the electrical resistance and lower energy consumption.
Currently, semiconductor wafers are usually thinned out mechanically by grinding. In this way, however, the thickness cannot be reduced beyond a certain limit, because the wafer must in any case maintain a sufficient mechanical resistance both during thinning-out and in the final machining steps. In particular, the mechanical stresses in the grinding step and in the cutting step can bring about microcracks in the wafer, and the likelihood of damage is all the greater the smaller the thickness achieved. In practice, the final thickness of the wafer can hardly fall below 100 μm without a reduction in the yield of the process.